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december 2007 rev 7 1/78 1 m29w128fh m29w128fl 128 mbit (8mb x 16 or 16mb x 8, page, uniform block) 3v supply flash memory feature summary supply voltage ?v cc = 2.7 to 3.6v for program, erase and read ?v pp =12v for fast program (optional) asynchronous random/page read ? page width: 8 words/16 bytes ? page access: 25, 30ns ? random access: 60, 70ns programming time ? 10s per byte/word (typical) ? 4 words / 8 bytes program ? 32-word (64-bytes) write buffer 64 kbyte (32 kword) uniform blocks program/ erase suspend and resume modes ? read from any block during program suspend ? read and program another block during erase suspend unlock bypass program ? faster production/batch programming common flash interface ? 64 bit security code 100,000 program/erase cycles per block low power consumption ? standby and automatic standby hardware block protection ?v pp /wp pin for fast program and write protect of the highest (m29w128fh) or lowest block (m29w128fl) extended memory block: extra block used as security block or to store additional information electronic signature ? manufacturer code: 0020h ? device code: m29w128fh: 227eh + 2212h + 228ah m29w128fl: 227eh + 2212h + 228bh ecopack ? packages bga tsop56 (n) 14 x 20mm tbga64 (za) 10 x 13mm www.numonyx.com
contents m29w128fh, m29w128fl 2/78 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 address inputs (a0-a22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 data inputs/outputs (dq8-dq14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 data input/output or address input (dq15a-1) . . . . . . . . . . . . . . . . . . . . 12 2.5 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 output enable (g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 v pp/ write protect (v pp/ wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 reset/block temporary unprotect (rp) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 ready/busy output (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 byte/word organization select (byte) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 v cc supply voltage (2.7v to 3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.1 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.2 verify extended memory block protection indicator . . . . . . . . . . . . . . . 17 3.6.3 verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.4 hardware block protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.5 temporary unprotect of high voltage protected blocks . . . . . . . . . . . . . 18 4 hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m29w128fh, m29w128fl contents 3/78 4.2 temporary block unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.3 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.4 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.6 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.8 program suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.9 program resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.10 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1 write to buffer and program command . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.2 write to buffer and program confirm command . . . . . . . . . . . . . . . . . . 29 5.2.3 write to buffer and program abort and reset command . . . . . . . . . . . 29 5.2.4 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.5 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.6 double byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.7 quadruple byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.8 octuple byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.9 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.10 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.11 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 extended memory block protection commands . . . . . . . . . . . . . . . . . . . 34 5.3.1 enter extended memory block command . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 exit extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.0.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.0.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.0.6 write to buffer and program abort bit (dq1) . . . . . . . . . . . . . . . . . . . . 38
contents m29w128fh, m29w128fl 4/78 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 appendix a block addresses and read/modify protection groups . . . . . . . . . 54 appendix b common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 appendix c extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 c.1 factory locked extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . 67 c.2 customer lockable extended memory block . . . . . . . . . . . . . . . . . . . . . . 68 appendix d high voltage block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 d.1 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 d.2 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 appendix e flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
m29w128fh, m29w128fl list of tables 5/78 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. read electronic signature, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. block protection, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. bus operations, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. read electronic signature, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. block protection, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 10. standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 11. fast program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. fast program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. extended block protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. block protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . 36 table 16. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. tsop56 ? 56 lead plastic thin small outline, 14 x 20mm, package mechanical data . . . 51 table 26. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 52 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. block addresses and protection groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 30. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 31. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 32. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 33. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 34. security code area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 35. extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 36. programmer technique bus operations, 8-bit or 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . 70 table 37. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
list of figures m29w128fh, m29w128fl 6/78 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6. toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 9. random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 10. page read ac waveforms (word mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 11. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 12. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13. reset/block temporary unprotect ac waveforms (no program/erase ongoing) . . . . . . . 49 figure 14. reset/block temporary unprotect during program/erase operation ac waveforms . . . . . 49 figure 15. accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. tsop56 ? 56 lead plastic thin small outline, 14 x 20mm, package outline . . . . . . . . . . . 51 figure 17. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 52 figure 18. programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 19. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 20. in-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 21. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 22. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 75
m29w128fh, m29w128fl summary description 7/78 1 summary description the m29w128fh and m29w128fl are 128 mbit (16mb x8 or 8mb x16) non-volatile memories that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. at power-up the memories default to read mode. the m29w128fh and m29w128fl are divided into 256 thirty-two kword (sixty-four kbyte) uniform blocks. program and erase commands are written to the command interface of the memory. an on- chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the chip enable, output enable and write enable signals control the bus operations of the memory. they allow simple connection to most microprocessors, often without additional logic. the devices support asynchronous random read and page read from all blocks of the memory array. the m29w128fh and m29w128fl have an extra 128 word (256 byte) extended memory block that can be accessed using a dedicated command. the extended memory block can be protected and so is useful for storing security information. however the protection is irreversible, once protected the protection cannot be undone. each block can be erased independently, so it is possible to preserve valid data while old data is erased. the devices feature two different levels of hardware block protection to avoid unwanted program or erase (modify): the v pp /wp pin protects the highest block on the m29w128fh and the lowest block on the m29w128fl. the rp pin temporarily unprotects all the blocks previously protected using a high voltage block protection technique (see appendix d: high voltage block protection ). the memories are offered in tsop56 (14 x 20mm) and tbga64 (10 x 13mm, 1mm pitch) packages. in order to meet environmental requirements, numonyx offers the m29w128fh and the m29w128fl in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. the memories are supplied with all the bits erased (set to ?1?). the m29w128fh and the m29w128fl will be referred to as m29w128f throughout the document. table 1. signal names a0-a22 address inputs
summary description m29w128fh, m29w128fl 8/78 figure 1. logic diagram 1. also see appendix a and table 28 for a full listing of the block addresses. dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a ? 1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v pp /wp v pp /write protect v ss ground nc not connected internally table 1. signal names ai11525 23 a0-a22 w dq0-dq14 v cc m29w128fh m29w128fl e v ss 15 g rp dq15a-1 rb v pp /wp byte
m29w128fh, m29w128fl summary description 9/78 figure 2. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a19 a8 dq13 a17 a12 dq14 a2 dq12 dq10 dq15a-1 v cc dq4 dq5 a7 dq7 v pp /wp a21 ai11526 m29w128fh m29w128fl 14 1 15 28 29 42 43 56 dq8 nc a20 a1 a18 a4 a5 dq1 dq11 g a14 a15 a16 a13 byte nc a22 v ss e a0 rp v ss a9 a10 a11 nc nc nc nc v cc
summary description m29w128fh, m29w128fl 10/78 figure 3. tbga connections (top view through package) 6 5 4 3 2 1 v ss a11 a10 a8 a9 dq3 dq11 dq10 a18 v pp / wp rb a0 a2 a4 a3 g nc nc nc dq2 dq1 dq9 dq8 a6 a17 a7 dq4 v cc dq12 dq5 a19 a21 rp w a5 dq0 nc nc v ss a1 a20 dq7 byte c b a e d f g h dq15 a-1 8 7 ai11527 nc a15 a14 a12 a13 dq6 dq13 dq14 nc a22 nc v ss a16 nc nc e nc nc v cc v cc
m29w128fh, m29w128fl summary description 11/78 figure 4. block addresses ai11528 (x8) address lines a22-a0, dq15a-1 64 kbytes ffffffh ff0000h 64 kbytes 00ffffh 000000h 64 kbytes 010000h total of 256 uniform blocks 01ffffh (x16) address lines a22-a0 32 kwords 7fffffh 7f8000h 32 kwords 007fffh 000000h 32 kwords 008000h 00ffffh
signal descriptions m29w128fh, m29w128fl 12/78 2 signal descriptions see figure 1: logic diagram , and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a22) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq7) the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. 2.3 data inputs/outputs (dq8-dq14) the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. 2.4 data input/output or address input (dq15a ? 1) when the device is in x16 bus mode, this pin behaves as a data input/output pin (as dq8- dq14). when the device is in x8 bus mode, this pin behaves as an address pin; dq15a ? 1 low will select the lsb of the addressed word, dq15a ? 1 high will select the msb. throughout the text consider references to the data input/output to include this pin when the device operates in x16 bus mode and references to the address inputs to include this pin when the device operates in x8 bus mode except when stated explicitly otherwise. 2.5 chip enable (e ) the chip enable pin, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.6 output enable (g ) the output enable pin, g , controls the bus read operation of the memory.
m29w128fh, m29w128fl signal descriptions 13/78 2.7 write enable (w ) the write enable pin, w , controls the bus write operation of the memory?s command interface. 2.8 v pp/ write protect (v pp /wp ) the v pp /write protect pin provides two functions. the v pp function allows the memory to use an external high voltage power supply to reduce the time required for program operations. this is achieved by bypassing the unlock cycles and/or using the multiple word (2 or 4 at-a-time) or multiple byte program (2, 4 or 8 at-a-time) commands. the write protect function provides a hardware method of protecting the highest or lowest block. when v pp /write protect is low, v il , the highest or lowest block is protected; program and erase operations on this block are ignored while v pp /write protect is low, even when rp is at v id . when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the highest or lowest block. program and erase operations can now modify the data in this block unless the block is protected using block protection. applying v pph to the v pp /wp pin will temporarily unprotect any block previously protected (including the highest or lowest block) using a high voltage block protection technique (in- system or programmer technique). see table 8: hardware protection for details. when v pp /write protect is raised to v pp the memory automatically enters the unlock bypass mode. when v pp /write protect returns to v ih or v il normal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pp and from v pp to v ih must be slower than t vhvpp (see figure 15: accelerated program timing waveforms ). never raise v pp /write protect to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. the v pp /write protect pin must not be left floating or unconnected or the device may become unreliable. a 0.1f capacitor should be connected between the v pp /write protect pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp .
signal descriptions m29w128fh, m29w128fl 14/78 2.9 reset/block temporary unprotect (rp ) the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all the blocks previously protected using a high voltage block protection technique (in-system or programmer technique). note that if v pp /wp is at v il , then the highest or lowest block will remain protected even if rp is at v id . a hardware reset is achieved by holding reset/block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see section 2.10: ready/busy output (rb) , table 24: reset/block temporary unprotect ac characteristics and figure 13 and figure 14 for more details. holding rp at v id will temporarily unprotect all the blocks previously protected using a high voltage block protection technique. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . 2.10 ready/busy output (rb ) the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol . ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table 24: reset/block temporary unprotect ac characteristics and figure 13 and figure 14 . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.11 byte/word organization select (byte ) it is used to switch between the x8 and x16 bus modes of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. 2.12 v cc supply voltage (2.7v to 3.6v) v cc provides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc2 .
m29w128fh, m29w128fl signal descriptions 15/78 2.13 v ss ground v ss is the reference for all voltage measurements. the device features two v ss pins both of which must be connected to the system ground.
bus operations m29w128fh, m29w128fl 16/78 3 bus operations there are five standard bus operations that control the device. these are bus read (random and page modes), bus write, output disable, standby and automatic standby. see ta b l e 2 and ta b l e 5 , bus operations, for a summary. typically glitches of less than 5ns on chip enable, write enable, and reset/block temporary unprotect pins are ignored by the memory and do not affect bus operations. 3.1 bus read bus read operations read from the memory cells, or specific registers in the command interface. to speed up the read operation the memory array can be read in page mode where data is internally read and stored in a page buffer. the page has a size of 8 words (or 16 bytes) and is addressed by the address inputs a2-a0 in x16 mode and a2-dq15a ? 1 in byte mode. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 9: random read ac waveforms , figure 10: page read ac waveforms (word mode) , and table 21: read ac characteristics , for details of when the output becomes valid. 3.2 bus write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figure 11 and figure 12 , write ac waveforms, and ta bl e 2 2 and ta b l e 2 3 , write ac characteristics, for details of the timing requirements. 3.3 output disable the data inputs/outputs are in the high impedance state when output enable is high, v ih . 3.4 standby when chip enable is high, v ih , the memory enters standby mode and the data inputs/outputs pins are placed in the high-impedance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.3v. for the standby current level see table 20: dc characteristics . during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations until the operation completes.
m29w128fh, m29w128fl bus operations 17/78 3.5 automatic standby if cmos levels (v cc 0.3v) are used to drive the bus and the bus is inactive for t avqv + 30ns or more the memory enters automatic standby where the internal supply current is reduced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. 3.6 special bus operations additional bus operations can be performed to read the electronic signature, verify the protection status of the extended memory block, and apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.6.1 read electronic signature the memory has two codes, the manufacturer code and the device code used to identify the memory. these codes can accessed by performing read operations with control signals and addresses set as shown in ta b l e 3 and ta b l e 5 . these codes can also be accessed by issuing an auto select command (see section 5.1.2: auto select command ). 3.6.2 verify extended memory block protection indicator the extended memory block is either factory locked or customer lockable. the protection status of the extended memory block (factory locked or customer lockable) can be accessed by reading the extended memory block protection indicator. this is performed by applying the signals as shown in ta b l e 4 and ta bl e 7 . the protection status of the extended memory block is then output on bit dq7 of the data input/outputs. (see ta bl e 2 and ta b l e 5 , bus operations). the protection status of the extended memory block can also be accessed by issuing an auto select command (see section 5.1.2: auto select command ). 3.6.3 verify bloc k protection status the protection status of a block can be directly accessed by performing a read operation with control signals and addresses set as shown in ta bl e 4 and ta b l e 7 . if the block is protected, then 01h (in x8 mode) is output on data input/outputs dq0-dq7, otherwise 00h is output. 3.6.4 hardware block protect the v pp /wp pin can be used to protect the highest or lowest block. when v pp /wp is at v il the highest or lowest block is protected and remains protected regardless of the block protection status or the reset/block temporary unprotect pin state.
bus operations m29w128fh, m29w128fl 18/78 3.6.5 temporary unprotect of high voltage protected blocks the rp pin can be used to temporarily unprotect all the blocks previously protected using the in-system or the programmer protection technique (high voltage techniques). refer to section 2.9: reset/block temporary unprotect (rp) . table 2. bus operations, 8-bit mode operation (1) e g w rp v pp /wp address inputs data inputs/outputs a22-a0, dq15a-1 dq14-dq8 dq7-dq0 bus read v il v il v ih v ih v ih cell address hi-z data output bus write v il v ih v il v ih v ih command address hi-z data input output disable x v ih v ih v ih v ih xhi-zhi-z standby v ih xxv ih v ih xhi-zhi-z 1. x = v il or v ih . table 3. read electronic signature, 8-bit mode read cycle (1) e g w address inputs data inputs/outputs a22-a10 a9 a8-a7 a6 a5-a4 a3 a2 a1 a0 dq15a-1 dq14- dq8 dq7-dq0 manufacturer code v il v il v ih xv id xv il x v il v il v il v il xhi-z 20h device code (cycle 1) v il v il v il v ih x hi-z 7eh (both devices) device code (cycle 2) v ih v ih v ih v il x hi-z 12h (both devices) device code (cycle 3) v ih v ih v ih v ih xhi-z 8ah (m29w128fh) 8bh (m29w128fl) 1. x = v il or v ih .
m29w128fh, m29w128fl bus operations 19/78 table 4. block protection, 8-bit mode operation (1) e g w rp v pp / wp address inputs data inputs/outputs a22- a12 a11- a10 a9 a8- a7 a6 a5- a4 a3- a2 a1 a0 dq15 a-1 dq14 -dq8 dq7-dq0 verify extended memory block protection indicator (bit dq7) v il v il v ih v ih v ih ba x v id xv il xv il v ih v ih x hi-z m29w128fh 88h (factory locked) 08h (customer lockable) m29w128fl 98h (factory locked) 18h (customer lockable) verify block protection status v il 01h (protected) 00h (unprotected) temporary block unprotect (2) xxxv id x valid data input 1. x = v il or v ih . ba any address in the block. 2. the rp pin unprotects all the blocks that have been previous ly protected using a high voltage protection technique. table 5. bus operations, 16-bit mode operation (1) e g w rp v pp / wp address inputs data inputs/outputs a22-a0 dq15a-1, dq14-dq0 bus read v il v il v ih v ih v ih cell address data output bus write v il v ih v il v ih v ih command address data input output disable x v ih v ih v ih v ih xhi-z standby v ih xxv ih v ih xhi-z 1. x = v il or v ih .
bus operations m29w128fh, m29w128fl 20/78 table 6. read electronic signature, 16-bit mode read cycle (1) e g w address inputs data inputs/outputs a22- a10 a9 a8- a7 a6 a5- a4 a3 a2 a1 a0 dq15a-1, dq14-dq0 manufacturer code v il v il v ih xv id xv il x v il v il v il v il 0020h device code (cycle 1) v il v il v il v ih 227eh (both devices) device code (cycle 2) v ih v ih v ih v il 2212h (both devices) device code (cycle 3) v ih v ih v ih v ih 228ah (m29w128fh) 228bh (m29w128fl) 1. x = v il or v ih . table 7. block protection, 16-bit mode operation (1) e g w rp v pp / wp address inputs data inputs/outputs a22- a12 a11- a10 a9 a8- a7 a6 a5- a4 a3- a2 a1 a0 dq15a-1, dq14-dq0 verify extended memory block indicator (bit dq7) v il v il v ih v ih v ih ba x v id xv il xv il v ih v ih m29w128fh 0088h (factory locked) 0008h (customer lockable) m29w128fl 0098h (factory locked) 0018h (customer lockable) verify block protection status v il 0001h (protected) 0000h (unprotected) temporary block unprotect (2) xx xv id x valid data input 1. x = v il or v ih . ba any address in the block. 2. the rp pin unprotects all the blocks that have been previous ly protected using a high voltage protection technique.
m29w128fh, m29w128fl hardware protection 21/78 4 hardware protection the m29w128f features hardware protection/unprotection. refer to ta bl e 8 for details on hardware block protection/unprotection using v pp /wp and rp pins. 4.1 write protect the v pp /wp pin protects the highest or lowest block (refer to section 2: signal descriptions for a detailed description of the signals). 4.2 temporary block unprotect when held at v id , the reset/block temporary unprotect pin, rp , will temporarily unprotect all the blocks previously protected using a high voltage block protection technique. table 8. hardware protection v pp /wp rp function v il v ih highest or lowest block protected from program/erase operations v id all blocks temporarily unprotected except the highest or lowest block v ih or v id v id all blocks temporarily unprotected v pph v ih or v id all blocks temporarily unprotected
command interface m29w128fh, m29w128fl 22/78 5 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will result in the memory returning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. 5.1 standard commands see either ta b l e 9 , or ta b l e 1 0 , depending on the configuration that is being used, for a summary of the standard commands. 5.1.1 read/reset command the read/reset command returns the memory to read mode. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. if the read/reset command is issued during the time-out of a block erase operation, the memory will take up to 10s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. 5.1.2 auto select command the auto select command is used to read the manufacturer code, the device code, the protection status of each block (block protection status) and the extended memory block protection indicator. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued bus read operations to specific addresses output the manufacturer code, the device code, the extended memory block protection indicator and a block protection status (see ta b l e 9 and ta b l e 1 0 in conjunction with ta b l e 3 , ta b l e 4 , ta b l e 6 and ta bl e 7 ). the memory remains in auto select mode until a read/reset or cfi query command is issued. 5.1.3 read cfi query command the read cfi query command is used to put the memory in read cfi query mode. once in read cfi query mode, bus read operations to the memory will output data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read cfi query command. this command is valid only when the device is in the read array or auto select mode. the read/reset command must be issued to return the device to the previous mode (the read array mode or auto select mode). a second read/reset command is required to put the device in read array mode from auto select mode.
m29w128fh, m29w128fl command interface 23/78 see appendix b , ta b l e 2 9 , ta bl e 3 0 , ta b l e 3 1 , ta b l e 3 2 , ta bl e 3 3 and ta b l e 3 4 for details on the information contained in the common flash interface (cfi) memory area. 5.1.4 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected, then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend command. it is not possible to issue any command to abort the operation. typical chip erase times are given in ta b l e 1 5 . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. 5.1.5 block erase command the block erase command can be used to erase a list of one or more blocks. it sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller after a time-out period of 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. after the sixth bus write operation, a bus read operation outputs the status register. see section 6: status register for details on how to identify if the program/erase controller has started the block erase operation. after the block erase operation has completed, the memory returns to the read mode, unless an error has occurred. when an error occurs, bus read operations will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command and the read/reset command which is only accepted during the 50s time-out period. typical block erase times are given in ta b l e 1 5 .
command interface m29w128fh, m29w128fl 24/78 5.1.6 erase suspend command the erase suspend command may be used to temporarily suspend a block or multiple block erase operation. one bus write operation is required to issue the command. issuing the erase suspend command returns the whole device to read mode. the program/erase controller will suspend within the erase suspend latency time (see table 15: program, erase times and program, erase endurance cycles ) of the erase suspend command being issued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. reading from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted. during erase suspend a bus read operation to the extended memory block will output the extended memory block data. once in the extended block mode, the exit extended block command must be issued before the erase operation can be resumed. 5.1.7 erase resume command the erase resume command is used to restart the program/erase controller after an erase suspend. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. 5.1.8 program suspend command the program suspend command allows the system to interrupt a program operation so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the program operation within the program suspend latency time (see table 15: program, erase times and program, erase endurance cycles ) and updates the status register bits. after the program operation has been suspended, the system can read array data from any address. however, data read from program-suspended addresses is not valid. the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the extended memory block area (one-time program area), the user must use the proper command sequences to enter and exit this region. the system may also issue the auto select command sequence when the device is in the program suspend mode. the system can read as many auto select codes as required.
m29w128fh, m29w128fl command interface 25/78 when the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. see auto select command sequence for more information. 5.1.9 program resume command after the program resume command is issued, the device reverts to programming. the controller can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to section 6: status register for details. the system must issue a program resume command, to exit the program suspend mode and to continue the programming operation. further issuing of the resume command is ignored. another program suspend command can be written after the device has resumed programming. 5.1.10 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 5.1.8: program suspend command and section 5.1.9: program resume command ). if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. after programming has started, bus read operations output the status register content. see section 6: status register for more details. typical program times are given in table 15: program, erase times and program, erase endurance cycles . after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs, bus read operations to the memory continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?.
command interface m29w128fh, m29w128fl 26/78 table 9. standard commands, 8-bit mode command length bus operations (1)(2) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3aaa aa55555 x f0 auto select manufacturer code 3 aaa aa 555 55 aaa 90 (3) (3) device code extended memory block protection indicator block protection status program 4 aaa aa 555 55 aaa a0 pa pd chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6 + aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase/program suspend 1 x b0 erase/program resume 1 x 30 read cfi query 1 aa 98 1. grey cells represent read cycles . the other cells are write cycles. 2. x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. 3. the auto select addresses and data are given in table 3: read electronic signature, 8-bit mode , and table 4: block protection, 8-bit mode , except for a9 that is ?don?t care?.
m29w128fh, m29w128fl command interface 27/78 table 10. standard commands, 16-bit mode command length bus operations (1)(2) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3555 aa2aa55 x f0 auto select manufacturer code 3 555 aa 2aa 55 555 90 (3) (3) device code extended memory block protection indicator block protection status program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase/program suspend 1 x b0 erase/program resume 1 x 30 read cfi query 1 55 98 1. gray cells represent read cycles . the other cells are write cycles. 2. x don?t care, pa program address, pd program data, ba an y address in the block. all values in the table are in hexadecimal. 3. the auto select addresses and data are given in table 6: read electronic signature, 16-bit mode , and table 7: block protection, 16-bit mode , except for a9 that is ?don?t care?.
command interface m29w128fh, m29w128fl 28/78 5.2 fast program commands the m29w128f offers a set of fast program commands to improve the programming throughput: write to buffer and program double and quadruple word, program double, quadruple and octuple byte program unlock bypass. see either ta b l e 1 2 , or ta b l e 1 1 , depending on the configuration that is being used, for a summary of the fast program commands. when v pph is applied to the v pp /write protect pin the memory automatically enters the fast program mode. the user can then choose to issue any of the fast program commands. care must be taken because applying a v pph to the v pp /wp pin will temporarily unprotect any protected block. after programming has started, bus read operations in the memory output the status register content. fast program commands can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 5.1.8: program suspend command and section 5.1.9: program resume command ) after the fast program operation has completed, the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. typical program times are given in table 15: program, erase times and program, erase endurance cycles . 5.2.1 write to buffer and program command the write to buffer and program command makes use of the device?s 64-byte write buffer to speed up programming. 32 words/64 bytes can be loaded into the write buffer. each write buffer has the same a22-a5 addresses.the write to buffer and program command dramatically reduces system programming time compared to the standard non-buffered program command. when issuing a write to buffer and program command, the v pp/ wp pin can be either held high, v ih or raised to v pph . see ta b l e 1 5 for details on typical write to buffer and program times in both cases. five successive steps are required to issue the write to buffer and program command: 1. the write to buffer and program command starts with two unlock cycles. 2. the third bus write cycle sets up the write to buffer and program command. the setup code can be addressed to any location within the targeted block. 3. the fourth bus write cycle sets up the number of words/bytes to be programmed. value n is written to the same block address, where n+1 is the number of words/bytes to be programmed. n+1 must not exceed the size of the write buffer or the operation will abort. 4. the fifth cycle loads the first address and data to be programmed.
m29w128fh, m29w128fl command interface 29/78 use n bus write cycles to load the address and data for each word/byte into the write buffer. addresses must lie within the range from the start address+1 to the start address + n-1. optimum performance is obtained when the start address corresponds to a 64 byte boundary. if the start address is not aligned to a 64 byte boundary, the total programming time is doubled. all the addresses used in the write to buffer and program operation must lie within the same page. to program the content of the write buffer, this command must be followed by a write to buffer and program confirm command. if an address is written several times during a write to buffer and program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the buffer. invalid address combinations or failing to follow the correct sequence of bus write cycles will abort the write to buffer and program. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer and program operation. if is not possible to detect program operation fails when changing programmed data from ?0? to ?1?, that is when reprogramming data in a portion of memory already programmed. the resulting data will be the logical or between the previous value and the current value. a write to buffer and program abort and reset command must be issued to abort the write to buffer and program operation and reset the device in read mode. see appendix e , figure 22: write to buffer and program flowchart and pseudo code , for a suggested flowchart on using the write to buffer and program command. 5.2.2 write to buffer and program confirm command the write to buffer and program confirm command is used to confirm a write to buffer and program command and to program the n+1 words/bytes loaded in the write buffer by this command. 5.2.3 write to buffer and pr ogram abort and reset command the write to buffer and program abort and reset command is used to abort write to buffer and program command. 5.2.4 double word program command this is used to write two adjacent words in x16 mode, simultaneously. the addresses of the two words must differ only in a0. three bus write cycles are necessary to issue the command: 1. the first bus cycle sets up the command. 2. the second bus cycle latches the address and the data of the first word to be written. 3. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller.
command interface m29w128fh, m29w128fl 30/78 5.2.5 quadruple word program command this is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode, simultaneously. the addresses of the four words must differ only in a1 and a0. five bus write cycles are necessary to issue the command: 1. the first bus cycle sets up the command. 2. the second bus cycle latches the address and the data of the first word to be written. 3. the third bus cycle latches the address and the data of the second word to be written. 4. the fourth bus cycle latches the address and the data of the third word to be written. 5. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. 5.2.6 double byte program command this is used to write two adjacent bytes in x8 mode, simultaneously. the addresses of the two bytes must differ only in dq15a-1. three bus write cycles are necessary to issue the command: 6. the first bus cycle sets up the command. 7. the second bus cycle latches the address and the data of the first byte to be written. 8. the third bus cycle latches the address and the data of the second byte to be written and starts the program/erase controller. 5.2.7 quadruple byte program command this is used to write four adjacent bytes in x8 mode, simultaneously. the addresses of the four bytes must differ only in a0, dq15a-1. five bus write cycles are necessary to issue the command. 1. the first bus cycle sets up the command. 2. the second bus cycle latches the address and the data of the first byte to be written. 3. the third bus cycle latches the address and the data of the second byte to be written. 4. the fourth bus cycle latches the address and the data of the third byte to be written. 5. the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/erase controller.
m29w128fh, m29w128fl command interface 31/78 5.2.8 octuple byte program command this is used to write eight adjacent bytes, in x8 mode, simultaneously. the addresses of the eight bytes must differ only in a1, a0 and dq15a-1. nine bus write cycles are necessary to issue the command: 1. the first bus cycle sets up the command. 2. the second bus cycle latches the address and the data of the first byte to be written. 3. the third bus cycle latches the address and the data of the second byte to be written. 4. the fourth bus cycle latches the address and the data of the third byte to be written. 5. the fifth bus cycle latches the address and the data of the fourth byte to be written. 6. the sixth bus cycle latches the address and the data of the fifth byte to be written. 7. the seventh bus cycle latches the address and the data of the sixth byte to be written. 8. the eighth bus cycle latches the address and the data of the seventh byte to be written. 9. the ninth bus cycle latches the address and the data of the eighth byte to be written and starts the program/erase controller. 5.2.9 unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long, considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been issued, the memory enters unlock bypass mode. when in unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. the unlock bypass program command can then be issued to program addresses within the memory, or the unlock bypass reset command can be issued to return the memory to read mode. in unlock bypass mode the memory can be read as if in read mode. 5.2.10 unlock bypa ss program command the unlock bypass program command can be used to program one address in the memory array at a time. the command requires two bus write operations, the final write operation latches the address and data and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. the operation cannot be aborted, a bus read operation to the memory outputs the status register. see the program command for details on the behavior. 5.2.11 unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode.
command interface m29w128fh, m29w128fl 32/78 table 11. fast program commands, 8-bit mode command length bus write operations (1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th add data add data add data add data add data add data add data add data add data write to buffer and program n +5 aaa aa 555 55 ba 25 ba n (2) pa (3) pd wbl (4) pd write to buffer and program abort and reset 3 aaa aa 555 55 aaa f0 write to buffer and program confirm 1ba (5) 29 double byte program 3 aaa 50 pa0 pd0 pa1 pd1 quadruple byte program 5 aaa 56 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 octuple byte program 9 aaa 8b pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 pa4 pd4 pa5 pd5 pa6 pd6 pa7 pd7 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2x a0 papd unlock bypass reset 2x 90 x 00 1. x don?t care, pa program address, pd program data, ba any address in the block, wbl write buffer location. all values in the table are in hexadecimal. 2. the maximum number of cycles in the command sequence is 68. n+1 is the number of bytes to be programmed during the write to b uffer and program operation. 3. each buffer has the same a22-a5 addresses. a0-a4 and a-1 are used to select a byte within the n+1 byte page. 4. the 6th cycle has to be issued n time. wbl scans the word inside the page. 5. ba must be identical to the address loaded during the write to buffer and program 3rd and 4th cycles.
m29w128fh, m29w128fl command interface 33/78 table 12. fast program commands, 16-bit mode command length bus write operations (1) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data write to buffer and program n+ 5 555 aa 2aa 55 ba 25 ba n (2) pa (3) pd wbl (4) pd write to buffer and program abort and reset 3 555 aa 2aa 55 555 f0 write to buffer and program confirm 1 ba (5) 29 double word program 3 555 50 pa0 pd0 pa1 pd1 quadruple word program 5 555 56 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 1. x don?t care, pa program address, pd program data, ba any ad dress in the block, wbl write buffer location. all values in the table are in hexadecimal. 2. the maximum number of cycles in the command sequence is 36. n+1 is the number of words to be programmed during the write to buffer and program operation. 3. each buffer has the same a22-a5 addresses. a0-a4 are used to select a word within the n+1 word page. 4. the 6th cycle has to be issued n time. wbl scans the word inside the page. 5. ba must be identical to the address loaded during the write to buffer and program 3rd and 4th cycles.
command interface m29w128fh, m29w128fl 34/78 5.3 extended memory block protection commands the m29w128f offers a set of commands to access the extended memory block and to configure and check its protection mode. the commands related to the extended memory block protection are available in both 8 bit and 16 bit memory configuration. 5.3.1 enter extended memory block command the m29w128f has one extra 128 word block (extended memory block) that can only be accessed using the enter extended memory block command. three bus write cycles are required to issue the extended memory block command. once the command has been issued the device enters the extended memory block mode where all bus read or program operations are conducted on the extended memory block. once the device is in the extended block mode, the extended memory block is addressed by using the addresses occupied by block 0 in the other operating modes (see ta b l e 2 8 : b l o ck addresses and protection groups ). the device remains in extended block mode until the exit extended block command is issued or power is removed from the device. after power-up or a hardware reset, the device reverts to the read mode where commands issued to block 0 address space will address block 0. note that when the device is in the extended block mode, the v pp /wp pin cannot be used for fast programming and the unlock bypass mode is not available. the extended memory block cannot be erased, and can be treated as one-time programmable (otp) memory. in extended block mode, erase, chip erase, erase suspend and erase resume commands are not allowed. to exit from the extended block mode the exit extended block command must be issued. the extended memory block can be protected by setting the extended memory block protection bit to ?1?; however once protected the protection cannot be undone. 5.3.2 exit extended block command the exit extended block command is used to exit from the extended block mode and return the device to read mode. four bus write operations are required to issue the command.
m29w128fh, m29w128fl command interface 35/78 table 13. extended block protection commands, 8-bit mode command length bus operations (1)(2) 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data enter extended block 3 aaa aa 555 55 aaa 88 exit extended block 4 aaa aa 555 55 aaa 90 x 00 1. x don?t care. all values in the table are in hexadecimal. 2. grey cells represent read cycles . the other cells are write cycles. table 14. block protection commands, 16-bit mode command length bus operations (1)(2)(3) 1st 2nd 3rd 4th 5th 6th 7th add data add data add data add data add data add data add data enter extended block 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00 1. grey cells represent read cycles . the other cells are write cycles. 2. x don?t care. all values in the table are in hexadecimal. 3. during command cycles, if the lower address bits are 555h or 2aah then the address bits higher than a11 and data bits higher than dq7 are don't care.
command interface m29w128fh, m29w128fl 36/78 table 15. program, erase times and program, erase endurance cycles parameter min typ (1)(2) max (2) unit chip erase 80 400 (3) s block erase (64 kbytes) 0.8 6 (4) s erase suspend latency time 50 (4) s byte program single or multiple byte program (1, 2, 4 or 8 bytes at-a-time) 10 200 (3) s write to buffer and program (64 bytes at-a-time) v pp /wp =v pph 90 s v pp /wp =v ih 280 word program single or multiple word program (1, 2 or 4 words at-a-time) 10 200 (3) s write to buffer and program (32 words at-a-time) v pp /wp = v pph 90 s v pp /wp =v ih 280 chip program (byte by byte) 80 400 (3) s chip program (word by word) 40 200 (3) s chip program (quadruple byte or double word) 20 100 (3) s chip program (octuple byte or quadruple word) 10 50 (3) s program suspend latency time 5 15 s program/erase cycles (per block) 100,000 cycles data retention 20 years 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. 4. maximum value measured at worst case conditions for both temperature and v cc .
m29w128fh, m29w128fl status register 37/78 6 status register the m29w128f has one status register. the status register provides information on the current or previous program or erase operations. the various bits convey information and errors on the operation. bus read operations from any address within the memory, always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table 16: status register bits . 6.0.1 data polling bit (dq7) the data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit outputs ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 5: data polling flowchart , gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 6.0.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during a program/erase operation the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any address. after successful completion of the operation the memory returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 6: toggle flowchart , gives an example of how to use the data toggle bit.
status register m29w128fh, m29w128fl 38/78 6.0.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that address will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 6.0.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 6.0.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not being erased will output the memory array data as if in read mode. after an erase operation that causes the error bit to be set, the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly. 6.0.6 write to buffer a nd program abort bit (dq1) the write to buffer and program abort bit, dq1, is set to ?1? when a write to buffer and program operation aborts. the write to buffer and program abort and reset command must be issued to return the device to read mode (see write to buffer and program in commands section).
m29w128fh, m29w128fl status register 39/78 figure 5. data polling flowchart table 16. status register bits (1) operation dq7 dq6 dq5 dq3 dq2 dq1 rb program dq7 toggle 0 ? ? 0 0 program during erase suspend dq7 toggle 0 ? ? ? 0 write to buffer and program abort dq7 toggle 0 ? ? 1 0 program error dq7 toggle 1 ? ? ? hi-z chip erase 0 toggle 0 1 toggle ? 0 block erase before timeout 0 toggle 0 0 toggle ? 0 0 toggle 0 0 no toggle ? 0 block erase 0 toggle 0 1 toggle ? 0 0 toggle 0 1 no toggle ? 0 erase suspend 1 no toggle 0 ? toggle ? hi-z data read as normal ? hi-z erase error 0 toggle 1 1 no toggle ? hi-z 0 toggle 1 1 toggle ? hi-z 1. unspecified data bits should be ignored. read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai07760 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
status register m29w128fh, m29w128fl 40/78 figure 6. toggle flowchart read dq6 at valid address start read dq6 twice at valid address fail pass ai11530 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6 at valid address
m29w128fh, m29w128fl maximum rating 41/78 7 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the numonyx sure program and other relevant quality documents. table 17. absolute maximum ratings symbol parameter min max unit t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io input or output voltage (1)(2) 1. minimum voltage may undershoot to ? 2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc + 2v during transition and for less than 20ns during transitions. ? 0.6 v cc + 0.6 v v cc supply voltage ? 0.6 4 v v id identification voltage ? 0.6 13.5 v v pp (3) 3. v pp must not remain at 12v for more than a total of 80hrs. program voltage ? 0.6 13.5 v
dc and ac parameters m29w128fh, m29w128fl 42/78 8 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 18: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 7. ac measurement load circuit table 18. operating and ac measurement conditions parameter m29w128fh, m29w128fl unit 60 70 minmaxminmax v cc supply voltage 2.7 3.6 2.7 3.6 v ambient operating temperature ? 40 85 ? 40 85 c load capacitance (c l )3030pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai05558 c l c l includes jig capacitance device under test 25k v cc 25k v cc 0.1f v pp 0.1f
29 128?, 29 128? dc and ac parameters 43/78 figure 8. ac measurement i/o waveform table 19. device capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf table 20. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 (1) 1. sampled only, not 100% tested. supply current (program/erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp = v pph 20 ma v il input low voltage ? 0.5 0.8 v v ih input high voltage 0.7v cc v cc + 0.3 v v pph voltage for v pp /wp program acceleration v cc = 2.7v 10% 11.5 12.5 v i pp current for v pp /wp program acceleration v cc = 2.7v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ? 100 av cc ? 0.4 v v id identification voltage 11.5 12.5 v v lko program/erase lockout supply voltage 1.8 2.3 v ai05557 v cc 0v v cc /2
dc and ac parameters m29w128fh, m29w128fl 44/78 figure 9. random read ac waveforms ai08970 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a22/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29w128fh, m29w128fl dc and ac parameters 45/78 figure 10. page read ac waveforms (word mode) ai08971c tehqz tghqx valid a3-a22 a-1 g dq0-dq15 e telqv tehqx tghqz valid a0-a2 valid valid valid valid valid valid valid tglqv tavqv tavqv1 valid valid valid valid valid valid valid valid
dc and ac parameters m29w128fh, m29w128fl 46/78 table 21. read ac characteristics symbol alt parameter test condition m29w128fh, m29w128fl unit 60 70 t avav t rc address valid to next address valid e = v il , g = v il min 60 70 ns t avqv t acc address valid to output valid e = v il , g = v il max 60 70 ns t avqv1 t pag e address valid to output valid (page) e = v il , g = v il max 25 30 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 60 70 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 20 25 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 25 ns t ghqz (1) t df output enable high to output hi-z e = v il max 25 25 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 25 25 ns t bhqv t fhqv byte high to output valid max 30 30 ns 1. sampled only, not 100% tested.
m29w128fh, m29w128fl dc and ac parameters 47/78 figure 11. write ac waveforms, write enable controlled ai08972 e g w a0-a22/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl table 22. write ac characteristics, write enable controlled symbol alt parameter m29w128fh, m29w128fl unit 60 70 t avav t wc address valid to next address valid min 60 70 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 45 ns t dvwh t ds input valid to write enable high min 45 45 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 45 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 30 ns t vchel t vcs v cc high to chip enable low min 50 50 s 1. sampled only, not 100% tested.
dc and ac parameters m29w128fh, m29w128fl 48/78 figure 12. write ac waveforms, chip enable controlled ai08973 e g w a0-a22/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl table 23. write ac characteristics, chip enable controlled symbol alt parameter m29w128fh, m29w128fl unit 60 70 t avav t wc address valid to next address valid min 60 70 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t dveh t ds input valid to chip enable high min 45 45 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 45 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 30 ns t vchwl t vcs v cc high to write enable low min 50 50 s 1. sampled only, not 100% tested.
m29w128fh, m29w128fl dc and ac parameters 49/78 figure 13. reset/block temporary unprotect ac waveforms (no program/erase ongoing) figure 14. reset/block temporary unprotect during program/erase operation ac waveforms ai11300b rb rp tplpx tphel, tphgl e, g ai11301b rb rp tplpx trhel, trhgl e, g tplyh table 24. reset/block temporary unprotect ac characteristics symbol alt parameter m29w128fh, m29w128fl unit 60 70 t plyh (1) t ready rp low to read mode, during program or erase max 20 s t plpx t rp rp pulse width min 500 ns t phel, t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 ns t rpd rp low to standby mode. min 20 ns t rhel t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 ns 1. sampled only, not 100% tested.
dc and ac parameters m29w128fh, m29w128fl 50/78 figure 15. accelerated program timing waveforms ai05563 v pp /wp v pp v il or v ih tvhvpp tvhvpp
m29w128fh, m29w128fl package mechanical 51/78 9 package mechanical figure 16. tsop56 ? 56 lead plastic thin small outline, 14 x 20mm, package outline 1. drawing is not to scale. table 25. tsop56 ? 56 lead plastic thin small outline, 14 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 20.000 19.800 20.200 0.7874 0.7795 0.7953 d1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? e 14.000 13.900 14.100 0.5512 0.5472 0.5551 l 0.600 0.500 0.700 0.0236 0.0197 0.0276 3 0 5 3 0 5 n56 56 tsop-b d1 e 1 n cp b e a2 a n/2 d die c l a1
package mechanical m29w128fh, m29w128fl 52/78 figure 17. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package outline 1. drawing is not to scale. table 26. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.800 0.0315 b 0.350 0.500 0.0138 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 ? ? 0.2756 ? ? ddd 0.100 0.0039 e 1.000 ? ? 0.0394 ? ? e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 ? ? 0.2756 ? ? fd 1.500 ? ? 0.0591 ? ? fe 3.000 ? ? 0.1181 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ? e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m29w128fh, m29w128fl part numbering 53/78 10 part numbering note: this product is also available with the extended memory block factory locked. for further details and ordering information contact your nearest numonyx sales office. devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest numonyx sales office. table 27. ordering information scheme example: m29w128fh 70 n 6 f device type m29 operating voltage w = v cc = 2.7 to 3.6v device function 128fh = 128 mbit (x8/x16), page, uniform block, flash memory, highest block protected by v pp /wp 128fl = 128 mbit (x8/x16), page, uniform block, flash memory, lowest block protected by v pp /wp speed 60 = 60ns 70 = 70ns package n = tsop56: 14 x 20 mm za = tbga64: 10 x13mm, 1mm pitch temperature range 6 = ?40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape & reel packing
block addresses and read/modify protection groups m29w128fh, m29w128fl 54/78 appendix a block addresses and read/modify protection groups table 28. block addresses and protection groups block size (kbytes/kwords) protection block group (x8) (x16) 0 64/32 protection group 000000h-00ffffh 000000h-007fffh 1 64/32 protection group 010000h-01ffffh 008000h-00ffffh 2 64/32 protection group 020000h-02ffffh 010000h-017fffh 3 64/32 protection group 030000h-03ffffh 018000h-01ffffh 4 64/32 protection group 040000h-04ffffh 020000h-027fffh 5 64/32 050000h-05ffffh 028000h-02ffffh 6 64/32 060000h-06ffffh 030000h-037fffh 7 64/32 070000h-07ffffh 038000h-03ffffh 8 64/32 protection group 080000h-08ffffh 040000h-047fffh 9 64/32 090000h-09ffffh 048000h-04ffffh 10 64/32 0a0000h-0affffh 050000h-057fffh 11 64/32 0b0000h-0bffffh 058000h-05ffffh 12 64/32 protection group 0c0000h-0cffffh 060000h-067fffh 13 64/32 0d0000h-0dffffh 068000h-06ffffh 14 64/32 0e0000h-0effffh 070000h-077fffh 15 64/32 0f0000h-0fffffh 078000h-07ffffh 16 64/32 protection group 100000h-10ffffh 080000h-087fffh 17 64/32 110000h-11ffffh 088000h-08ffffh 18 64/32 120000h-12ffffh 090000h-097fffh 19 64/32 130000h-13ffffh 098000h-09ffffh 20 64/32 protection group 140000h-14ffffh 0a0000h-0a7fffh 21 64/32 150000h-15ffffh 0a8000h-0affffh 22 64/32 160000h-16ffffh 0b0000h-0b7fffh 23 64/32 170000h-17ffffh 0b8000h-0bffffh 24 64/32 protection group 180000h-18ffffh 0c0000h-0c7fffh 25 64/32 190000h-19ffffh 0c8000h-0cffffh 26 64/32 1a0000h-1affffh 0d0000h-0d7fffh 27 64/32 1b0000h-1bffffh 0d8000h-0dffffh
m29w128fh, m29w128fl block addresses and read/modify protection groups 55/78 28 64/32 protection group 1c0000h-1cffffh 0e0000h-0e7fffh 29 64/32 1d0000h-1dffffh 0e8000h-0effffh 30 64/32 1e0000h-1effffh 0f0000h-0f7fffh 31 64/32 1f0000h-1fffffh 0f8000h-0fffffh 32 64/32 protection group 200000h-20ffffh 100000h-107fffh 33 64/32 210000h-21ffffh 108000h?10ffffh 34 64/32 220000h-22ffffh 110000h?117fffh 35 64/32 230000h-23ffffh 118000h?11ffffh 36 64/32 protection group 240000h-24ffffh 120000h?127fffh 37 64/32 250000h-25ffffh 128000h?12ffffh 38 64/32 260000h-26ffffh 130000h?137fffh 39 64/32 270000h-27ffffh 138000h?13ffffh 40 64/32 protection group 280000h-28ffffh 140000h?147fffh 41 64/32 290000h-29ffffh 148000h?14ffffh 42 64/32 2a0000h-2affffh 150000h?157fffh 43 64/32 2b0000h-2bffffh 158000h?15ffffh 44 64/32 protection group 2c0000h-2cffffh 160000h?167fffh 45 64/32 2d0000h-2dffffh 168000h?16ffffh 46 64/32 2e0000h-2effffh 170000h?177fffh 47 64/32 2f0000h-2fffffh 178000h?17ffffh 48 64/32 protection group 300000h-30ffffh 180000h?187fffh 49 64/32 310000h-31ffffh 188000h?18ffffh 50 64/32 320000h-32ffffh 190000h?197fffh 51 64/32 330000h-33ffffh 198000h?19ffffh 52 64/32 protection group 340000h-34ffffh 1a0000h?1a7fffh 53 64/32 350000h-35ffffh 1a8000h?1affffh 54 64/32 360000h-36ffffh 1b0000h?1b7fffh 55 64/32 370000h-37ffffh 1b8000h?1bffffh 56 64/32 protection group 380000h-38ffffh 1c0000h?1c7fffh 57 64/32 390000h-39ffffh 1c8000h?1cffffh 58 64/32 3a0000h-3affffh 1d0000h?1d7fffh 59 64/32 3b0000h-3bffffh 1d8000h?1dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
block addresses and read/modify protection groups m29w128fh, m29w128fl 56/78 60 64/32 protection group 3c0000h-3cffffh 1e0000h?1e7fffh 61 64/32 3d0000h-3dffffh 1e8000h?1effffh 62 64/32 3e0000h-3effffh 1f0000h?1f7fffh 63 64/32 3f0000h-3fffffh 1f8000h?1fffffh 64 64/32 protection group 400000h-40ffffh 200000h?207fffh 65 64/32 410000h-41ffffh 208000h?20ffffh 66 64/32 420000h-42ffffh 210000h?217fffh 67 64/32 430000h-43ffffh 218000h?21ffffh 68 64/32 protection group 440000h-44ffffh 220000h?227fffh 69 64/32 450000h-45ffffh 228000h?22ffffh 70 64/32 460000h-46ffffh 230000h?237fffh 71 64/32 470000h-47ffffh 238000h?23ffffh 72 64/32 protection group 480000h-48ffffh 240000h?247fffh 73 64/32 490000h-49ffffh 248000h?24ffffh 74 64/32 4a0000h-4affffh 250000h?257fffh 75 64/32 4b0000h-4bffffh 258000h?25ffffh 76 64/32 protection group 4c0000h-4cffffh 260000h?267fffh 77 64/32 4d0000h-4dffffh 268000h?26ffffh 78 64/32 4e0000h-4effffh 270000h?277fffh 79 64/32 4f0000h-4fffffh 278000h?27ffffh 80 64/32 protection group 500000h-50ffffh 280000h?287fffh 81 64/32 510000h-51ffffh 288000h?28ffffh 82 64/32 520000h-52ffffh 290000h?297fffh 83 64/32 530000h-53ffffh 298000h?29ffffh 84 64/32 protection group 540000h-54ffffh 2a0000h?2a7fffh 85 64/32 550000h-55ffffh 2a8000h?2affffh 86 64/32 560000h-56ffffh 2b0000h?2b7fffh 87 64/32 570000h-57ffffh 2b8000h?2bffffh 88 64/32 protection group 580000h-58ffffh 2c0000h?2c7fffh 89 64/32 590000h-59ffffh 2c8000h?2cffffh 90 64/32 5a0000h-5affffh 2d0000h?2d7fffh 91 64/32 5b0000h-5bffffh 2d8000h?2dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
m29w128fh, m29w128fl block addresses and read/modify protection groups 57/78 92 64/32 protection group 5c0000h-5cffffh 2e0000h?2e7fffh 93 64/32 5d0000h-5dffffh 2e8000h?2effffh 94 64/32 5e0000h-5effffh 2f0000h?2f7fffh 95 64/32 5f0000h-5fffffh 2f8000h?2fffffh 96 64/32 protection group 600000h-60ffffh 300000h?307fffh 97 64/32 610000h-61ffffh 308000h?30ffffh 98 64/32 620000h-62ffffh 310000h?317fffh 99 64/32 630000h-63ffffh 318000h?31ffffh 100 64/32 protection group 640000h-64ffffh 320000h?327fffh 101 64/32 650000h-65ffffh 328000h?32ffffh 102 64/32 660000h-66ffffh 330000h?337fffh 103 64/32 670000h-67ffffh 338000h?33ffffh 104 64/32 protection group 680000h-68ffffh 340000h?347fffh 105 64/32 690000h-69ffffh 348000h?34ffffh 106 64/32 6a0000h-6affffh 350000h?357fffh 107 64/32 6b0000h-6bffffh 358000h?35ffffh 108 64/32 protection group 6c0000h-6cffffh 360000h?367fffh 109 64/32 6d0000h-6dffffh 368000h?36ffffh 110 64/32 6e0000h-6effffh 370000h?377fffh 111 64/32 6f0000h-6fffffh 378000h?37ffffh 112 64/32 protection group 700000h?70ffffh 380000h?387fffh 113 64/32 710000h?71ffffh 388000h?38ffffh 114 64/32 720000h?72ffffh 390000h?397fffh 115 64/32 730000h?73ffffh 398000h?39ffffh 116 64/32 protection group 740000h?74ffffh 3a0000h?3a7fffh 117 64/32 750000h?75ffffh 3a8000h?3affffh 118 64/32 760000h?76ffffh 3b0000h?3b7fffh 119 64/32 770000h?77ffffh 3b8000h?3bffffh 120 64/32 protection group 780000h?78ffffh 3c0000h?3c7fffh 121 64/32 790000h?79ffffh 3c8000h?3cffffh 122 64/32 7a0000h?7affffh 3d0000h?3d7fffh 123 64/32 7b0000h?7bffffh 3d8000h?3dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
block addresses and read/modify protection groups m29w128fh, m29w128fl 58/78 124 64/32 protection group 7c0000h?7cffffh 3e0000h?3e7fffh 125 64/32 7d0000h?7dffffh 3e8000h?3effffh 126 64/32 7e0000h?7effffh 3f0000h?3f7fffh 127 64/32 7f0000h-7fffffh 3f8000h-3fffffh 128 64/32 protection group 800000h?80ffffh 400000h?407fffh 129 64/32 810000h?81ffffh 408000h?40ffffh 130 64/32 820000h?82ffffh 410000h?417fffh 131 64/32 830000h?83ffffh 418000h?41ffffh 132 64/32 protection group 840000h?84ffffh 420000h?427fffh 133 64/32 850000h?85ffffh 428000h?42ffffh 134 64/32 860000h?86ffffh 430000h?437fffh 135 64/32 870000h?87ffffh 438000h?43ffffh 136 64/32 protection group 880000h?88ffffh 440000h?447fffh 137 64/32 890000h?89ffffh 448000h?44ffffh 138 64/32 8a0000h?8affffh 450000h?457fffh 139 64/32 8b0000h?8bffffh 458000h?45ffffh 140 64/32 protection group 8c0000h?8cffffh 460000h?467fffh 141 64/32 8d0000h?8dffffh 468000h?46ffffh 142 64/32 8e0000h?8effffh 470000h?477fffh 143 64/32 8f0000h-8fffffh 478000h?47ffffh 144 64/32 protection group 900000h-90ffffh 480000h?487fffh 145 64/32 910000h?91ffffh 488000h?48ffffh 146 64/32 920000h?92ffffh 490000h?497fffh 147 64/32 930000h?93ffffh 498000h?49ffffh 148 64/32 protection group 940000h?94ffffh 4a0000h?4a7fffh 149 64/32 950000h?95ffffh 4a8000h?4affffh 150 64/32 960000h?96ffffh 4b0000h?4b7fffh 151 64/32 970000h?97ffffh 4b8000h?4bffffh 152 64/32 protection group 980000h?98ffffh 4c0000h?4c7fffh 153 64/32 990000h?99ffffh 4c8000h?4cffffh 154 64/32 9a0000h?9affffh 4d0000h?4d7fffh 155 64/32 9b0000h?9bffffh 4d8000h?4dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
m29w128fh, m29w128fl block addresses and read/modify protection groups 59/78 156 64/32 protection group 9c0000h?9cffffh 4e0000h?4e7fffh 157 64/32 9d0000h?9dffffh 4e8000h?4effffh 158 64/32 9e0000h?9effffh 4f0000h?4f7fffh 159 64/32 9f0000h?9fffffh 4f8000h-4fffffh 160 64/32 protection group a00000h?a0ffffh 500000h?507fffh 161 64/32 a10000h?a1ffffh 508000h?50ffffh 162 64/32 a20000h?a2ffffh 510000h?517fffh 163 64/32 a30000h?a3ffffh 518000h?51ffffh 164 64/32 protection group a40000h?a4ffffh 520000h?527fffh 165 64/32 a50000h?a5ffffh 528000h?52ffffh 166 64/32 a60000h?a6ffffh 530000h?537fffh 167 64/32 a70000h?a7ffffh 538000h?53ffffh 168 64/32 protection group a80000h?a8ffffh 540000h?547fffh 169 64/32 a90000h?a9ffffh 548000h?54ffffh 170 64/32 aa0000h?aaffffh 550000h?557fffh 171 64/32 ab0000h?abffffh 558000h?55ffffh 172 64/32 protection group ac0000h?acffffh 560000h?567fffh 173 64/32 ad0000h?adffffh 568000h?56ffffh 174 64/32 ae0000h?aeffffh 570000h?577fffh 175 64/32 af0000h-afffffh 578000h?57ffffh 176 64/32 protection group b00000h?b0ffffh 580000h?587fffh 177 64/32 b10000h?b1ffffh 588000h?58ffffh 178 64/32 b20000h?b2ffffh 590000h?597fffh 179 64/32 b30000h-b3ffffh 598000h?59ffffh 180 64/32 protection group b40000h?b4ffffh 5a0000h?5a7fffh 181 64/32 b50000h?b5ffffh 5a8000h?5affffh 182 64/32 b60000h?b6ffffh 5b0000h?5b7fffh 183 64/32 b70000h-b7ffffh 5b8000h?5bffffh 184 64/32 protection group b80000h?b8ffffh 5c0000h?5c7fffh 185 64/32 b90000h?b9ffffh 5c8000h?5cffffh 186 64/32 ba0000h?baffffh 5d0000h?5d7fffh 187 64/32 bb0000h?bbffffh 5d8000h?5dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
block addresses and read/modify protection groups m29w128fh, m29w128fl 60/78 188 64/32 protection group bc0000h?bcffffh 5e0000h?5e7fffh 189 64/32 bd0000h?bdffffh 5e8000h?5effffh 190 64/32 be0000h?beffffh 5f0000h?5f7fffh 191 64/32 bf0000h?bfffffh 5f8000h-5fffffh 192 64/32 protection group c00000h?c0ffffh 600000h?607fffh 193 64/32 c10000h?c1ffffh 608000h?60ffffh 194 64/32 c20000h?c2ffffh 610000h?617fffh 195 64/32 c30000h?c3ffffh 618000h?61ffffh 196 64/32 protection group c40000h?c4ffffh 620000h?627fffh 197 64/32 c50000h?c5ffffh 628000h?62ffffh 198 64/32 c60000h?c6ffffh 630000h?637fffh 199 64/32 c70000h-c7ffffh 638000h?63ffffh 200 64/32 protection group c80000h?c8ffffh 640000h?647fffh 201 64/32 c90000h?c9ffffh 648000h?64ffffh 202 64/32 ca0000h?caffffh 650000h?657fffh 203 64/32 cb0000h?cbffffh 658000h?65ffffh 204 64/32 protection group cc0000h?ccffffh 660000h?667fffh 205 64/32 cd0000h?cdffffh 668000h?66ffffh 206 64/32 ce0000h?ceffffh 670000h?677fffh 207 64/32 cf0000h-cfffffh 678000h?67ffffh 208 64/32 protection group d00000h?d0ffffh 680000h?687fffh 209 64/32 d10000h?d1ffffh 688000h?68ffffh 210 64/32 d20000h?d2ffffh 690000h?697fffh 211 64/32 d30000h?d3ffffh 698000h?69ffffh 212 64/32 protection group d40000h?d4ffffh 6a0000h?6a7fffh 213 64/32 d50000h?d5ffffh 6a8000h?6affffh 214 64/32 d60000h?d6ffffh 6b0000h?6b7fffh 215 64/32 d70000h-d7ffffh 6b8000h?6bffffh 216 64/32 protection group d80000h-d8ffffh 6c0000h?6c7fffh 217 64/32 d90000h-d9ffffh 6c8000h?6cffffh 218 64/32 da0000h-daffffh 6d0000h?6d7fffh 219 64/32 db0000h-dbffffh 6d8000h?6dffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
m29w128fh, m29w128fl block addresses and read/modify protection groups 61/78 220 64/32 protection group dc0000h-dcffffh 6e0000h?6e7fffh 221 64/32 dd0000h-ddffffh 6e8000h?6effffh 222 64/32 de0000h-deffffh 6f0000h?6f7fffh 223 64/32 df0000h-dfffffh 6f8000h-6fffffh 224 64/32 protection group e00000h-e0ffffh 700000h?707fffh 225 64/32 e10000h-e1ffffh 708000h?70ffffh 226 64/32 e20000h-e2ffffh 710000h?717fffh 227 64/32 e30000h-e3ffffh 718000h?71ffffh 228 64/32 protection group e40000h-e4ffffh 720000h?727fffh 229 64/32 e50000h-e5ffffh 728000h?72ffffh 230 64/32 e60000h-e6ffffh 730000h?737fffh 231 64/32 e70000h-e7ffffh 738000h?73ffffh 232 64/32 protection group e80000h-e8ffffh 740000h?747fffh 233 64/32 e90000h-e9ffffh 748000h?74ffffh 234 64/32 ea0000h-eaffffh 750000h?757fffh 235 64/32 eb0000h-ebffffh 758000h?75ffffh 236 64/32 protection group ec0000h-ecffffh 760000h?767fffh 237 64/32 ed0000h-edffffh 768000h?76ffffh 238 64/32 ee0000h-eeffffh 770000h?777fffh 239 64/32 ef0000h-efffffh 778000h?77ffffh 240 64/32 protection group f00000h-f0ffffh 780000h?787fffh 241 64/32 f10000h-f1ffffh 788000h?78ffffh 242 64/32 f20000h-f2ffffh 790000h?797fffh 243 64/32 f30000h-f3ffffh 798000h?79ffffh 244 64/32 protection group f40000h-f4ffffh 7a0000h?7a7fffh 245 64/32 f50000h-f5ffffh 7a8000h?7affffh 246 64/32 f60000h-f6ffffh 7b0000h?7b7fffh 247 64/32 f70000h-f7ffffh 7b8000h?7bffffh 248 64/32 protection group f80000h-f8ffffh 7c0000h?7c7fffh 249 64/32 f90000h-f9ffffh 7c8000h?7cffffh 250 64/32 fa0000h-faffffh 7d0000h?7d7fffh 251 64/32 fb0000h-fbffffh 7d8000h?7dffffh 252 64/32 protection group fc0000h-fcffffh 7e0000h?7e7fffh 253 64/32 protection group fd0000h-fdffffh 7e8000h?7effffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
block addresses and read/modify protection groups m29w128fh, m29w128fl 62/78 254 64/32 protection group fe0000h-feffffh 7f0000h?7f7fffh 255 64/32 protection group ff0000h-ffffffh 7f8000h?7fffffh table 28. block addresses and protection groups (continued) block size (kbytes/kwords) protection block group (x8) (x16)
m29w128fh, m29w128fl common flash interface (cfi) 63/78 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued, the memory enters read cfi query mode and read operations output the cfi data. ta bl e 2 9 , ta b l e 3 0 , ta b l e 3 1 , ta b l e 3 2 , ta bl e 3 3 and ta b l e 3 4 show the addresses (a-1, a0-a10) used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is written (see table 34: security code area ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. table 29. query structure overview (1) address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64 bit unique device number 1. query data are always presented on the lowest order data outputs. table 30. cfi query identification string (1) address data description value x16 x8 10h 20h 0051h ?q? 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see ta b l e 3 3 )p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h 1. query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are ?0?.
common flash interface (cfi) m29w128fh, m29w128fl 64/78 table 31. cfi query system interface information (1) address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100mv 3.0v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100mv 3.6v 1dh 3ah 00b5h v pp [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100mv 11.5v 1eh 3ch 00c5h v pp [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 10mv 12.5v 1fh 3eh 0004h typical timeout per single byte/word program = 2 n s 16s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 42h 0009h typical timeout per individual block erase = 2 n ms 512ms 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0005h maximum timeout for byte/word program = 2 n times typical 512s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0004h maximum timeout per individual block erase = 2 n times typical 8s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na 1. the values given in the above table are valid for both packages. table 32. device geometry definition address data description value x16 x8 27h 4eh 0018h device size = 2 n in number of bytes 16 mbytes 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0006h 0000h maximum number of bytes in multiple-byte program or page= 2 n 64 2ch 58h 0001h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 1 2dh 2eh 5ah 5ch 00ffh 0000h erase block region 1 information number of erase blocks of identical size = 00ffh+1 256 2fh 30h 5eh 60h 0000h 0001h erase block region 1 information block size in region 1 = 0100h * 256 byte 64 kbytes
m29w128fh, m29w128fl common flash interface (cfi) 65/78 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information 0 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information 0 table 32. device geometry definition (continued) address data description value x16 x8 table 33. primary algorithm-specific extended query table (1) address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0033h minor version number, ascii "3" 45h 8ah 000ch address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) ye s 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of sectors in per group 1 48h 90h 0001h temporary block unprotect 00 = not supported, 01 = supported ye s 49h 92h 0006h block protect /unprotect 06 = m29w128fh/m29w128fl 6 4ah 94h 0000h simultaneous operations: not supported na 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported no 4ch 98h 0002h page mode, 00 = not supported, 02 = 8-word page 02 4dh 9ah 00b5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100mv 11.5v
common flash interface (cfi) m29w128fh, m29w128fl 66/78 4eh 9ch 00c5h v pp supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100mv 12.5v 4fh 9eh 0000h top/bottom boot block flag 00h = uniform device uniform + v pp /wp protecting highest or lowest block 50h a0h 0001h program suspend, 00 = not supported, 01 = supported yes 1. the values given in the above table are valid for both packages. table 33. primary algorithm-specific extended query table (continued) (1) address data description value x16 x8 table 34. security code area address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx
m29w128fh, m29w128fl extended memory block 67/78 appendix c extended memory block the m29w128f has an extra block, the extended memory block, that can be accessed using a dedicated command. this extended memory block is 128 words in x16 mode and 256 bytes in x8 mode. it is used as a security block (to provide a permanent security identification number) or to store additional information. the extended memory block is either factory locked or customer lockable, its status is indicated by bit dq7. this bit is permanently set to either ?1? or ?0? at the factory and cannot be changed. when set to ?1?, it indicates that the device is factory locked and the extended memory block is protected. when set to ?0?, it indicates that the device is customer lockable and the extended memory block is unprotected. bit dq7 being permanently locked to either ?1? or ?0? is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. bit dq7 is the most significant bit in the extended memory block verify indicator and a specific procedure must be followed to read it. see verify extended memory block protection indicator in table 4: block protection, 8-bit mode and table 7: block protection, 16-bit mode , for details of how to read bit dq7. the extended memory block can only be accessed when the device is in extended memory block mode. for details of how the extended block mode is entered and exited, refer to the section 5.3.1: enter extended memory block command and section 5.3.2: exit extended block command , and to ta b l e 1 3 and ta b l e 9 . c.1 factory locked extended memory block in devices where the extended memory block is factory locked, the security identification number is written to the extended memory block address space (see table 35: extended memory block address and data ) in the factory. the dq7 bit is set to ?1? and the extended memory block cannot be unprotected.
extended memory block m29w128fh, m29w128fl 68/78 c.2 customer lockable extended memory block a device where the extended memory block is customer lockable is delivered with the dq7 bit set to ?0? and the extended memory block unprotected. it is up to the customer to program and protect the extended memory block but care must be taken because the protection of the extended memory block is not reversible. there are two ways of protecting the extended memory block: issue the enter extended block command to place the device in extended block mode, then use the in-system technique with rp either at v ih or at v id (refer to appendix d: high voltage block protection , and to the corresponding flowcharts, figure 20 and figure 21 , for a detailed explanation of the technique). issue the enter extended block command to place the device in extended block mode, then use the programmer technique (refer to appendix d: high voltage block protection , and to the corresponding flowcharts, figure 18 and figure 19 , for a detailed explanation of the technique). once the extended memory block is programmed and protected, the exit extended block command must be issued to exit the extended memory block mode and return the device to read mode. table 35. extended memory block address and data address (1) data x8 x16 factory locked customer lockable 000000h-0000ffh 000000h-00007fh security identification number determined by customer 1. see table 28: block addresses and protection groups .
m29w128fh, m29w128fl high voltage block protection 69/78 appendix d high voltage block protection the high voltage block protection can be used to prevent any operation from modifying the data stored in the memory. the blocks are protected in groups, refer to appendix a: block addresses and read/modify protection groups , and ta b l e 2 8 for details of the protection groups. once protected, program and erase operations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. temporary unprotection is controlled by the reset/block temporary unprotection pin, rp ; this is described in the signal descriptions section. to protect the extended memory block issue the enter extended block command and then use either the programmer or in-system technique. once protected issue the exit extended block command to return to read mode. the extended memory block protection is irreversible, once protected the protection cannot be undone. d.1 programmer technique the programmer technique uses high (v id ) voltage levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 18: programmer equipment group protect flowchart . to unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 19: programmer equipment chip unprotect flowchart . table 36: programmer technique bus operations, 8-bit or 16-bit mode , gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
high voltage block protection m29w128fh, m29w128fl 70/78 d.2 in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp (1) . this can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. to protect a group of blocks follow the flowchart in figure 20: in-system equipment group protect flowchart . to unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 21: in-system equipment chip unprotect flowchart . the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. note: rp can be either at v ih or at v id when using the in-system technique to protect the extended memory block. table 36. programmer technique bus operations, 8-bit or 16-bit mode operation e g w address inputs a0-a22 data inputs/outputs dq15a?1, dq14-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a22 block address others = x x chip unprotect v id v id v il pulse a6 = v ih , a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protect verify v il v il v ih a0, a2, a3, a6 = v il , a1 = v ih a9 = v id , a12-a22= block address others = x pass = xx01h retry = xx00h. block (group) unprotect verify v il v il v ih a0, a2, a3 = v il a1, a6 = v ih a9 = v id , a12-a22 = block address others = x pass = xx00h retry = xx01h. 1. block protection groups are shown in appendix d , table 28 .
m29w128fh, m29w128fl flowcharts 71/78 appendix e flowcharts figure 18. programmer equipment group protect flowchart 1. block protection groups are shown in appendix d: high voltage block protection , table 28 . address = group address ai07756b g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a1 = v ih a0, a2 to a7 = v il a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
flowcharts m29w128fh, m29w128fl 72/78 figure 19. programmer equipment chip unprotect flowchart 1. block protection groups are shown in appendix d: high voltage block protection , table 28 . protect all groups ai07757b a6, a12, a15 = v ih (1) e, g, a9 = v id data = 00h w = v ih e, g = v ih address = current group address a0, a2, a3, a4, a5, a7 = v il a1, a6 = v ih wait 10ms increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
m29w128fh, m29w128fl flowcharts 73/78 figure 20. in-system equipment group protect flowchart 1. block protection groups are shown in appendix d: high voltage block protection , table 28 . 2. rp can be either at v ih or at v id when using the in-system technique to protect the extended memory block. ai07758b write 60h address = group address a0, a2, a3, a6 = v il, a1 = v ih n = 0 wait 100s write 40h address = group address a0, a2, a3, a6 = v il, a1 = v ih rp = v ih ++n = 25 start pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a1 = v ih , a0, a2 to a7 = v il rp = v id issue read/reset command write 60h address = group address a0, a2, a3, a6 = v il, a1 = v ih issue read/reset command fail
flowcharts m29w128fh, m29w128fl 74/78 figure 21. in-system equipment chip unprotect flowchart 1. block protection groups are shown in appendix d: high voltage block protection , table 28 . ai07759d write 60h any address with a0, a2, a3, a4, a5, a7 = v il a1, a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a1 = v ih , a0, a2 to a7 = v il rp = v ih ++n = 1000 start fail pass no data = 00h yes no rp = v ih wait 4s read data address = current group address a1 = v ih , a0, a2 to a7 = v il rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a1 = v ih , a0, a2 to a7 = v il verify unprotect set-up end yes
m29w128fh, m29w128fl flowcharts 75/78 figure 22. write to buffer and program flowchart and pseudo code 1. n+1 is the number of addresses to be programmed. write to buffer f0h command, block address ai08968b start write buffer data, start address yes abort write to buffer fail or abort (5) no write n (1) , block address x = 0 write next data, program address pair x = x-1 program buffer to flash block address read status register (dq1, dq5, dq7) at last loaded address yes dq7 = data no check status register (dq5, dq7) at last loaded address (3) no yes write to a different block address write to buffer and program aborted (2) no dq5 = 1 yes no dq1 = 1 yes yes dq7 = data (4) no end first part of the write to buffer and program command x=n
flowcharts m29w128fh, m29w128fl 76/78 2. a write to buffer and program abort and reset mu st be issued to return the device in read mode. 3. when the block address is specified, any address in the selected block addres s space is acceptable. however when loading write buffer address with data, all addresses must fall within the selected write buffer page. 4. dq7 must be checked since dq5 and dq7 may change simultaneously. 5. if this flowchart location is reached because dq5=?1?, then the write to buffer and program command failed. if this flowchart location is reached because dq1=?1?, then the write to buffer and program command aborted. in both cases, the appropriate reset command must be issued to return the device in read mode: a reset command if the operation failed, a write to buffer and program abort and reset command if the operation aborted. 6. see table 9 and table 10 , for details on write to buffer and program command sequence.
m29w128fh, m29w128fl revision history 77/78 revision history table 37. document revision history date version changes 29-sep-2005 0.1 first issue. 02-dec-2005 1 document status changed to ?full datasheet?. title updated. program suspend latency time updated in table 15: program, erase times and program, erase endurance cycles . 07-mar-2006 2 dq7 changed to dq7 for program, program during erase suspend and program error in table 16: status register bits . 13-mar-2006 3 section 5.2.1: write to buffer and program command , and section 5.2.2: write to buffer and program confirm command updated to cover 8-bit mode. note 2 , note 3 , and note 4 updated in table 11: fast program commands, 8-bit mode . 06-apr-2006 4 verify extended memory block protection bit command removed. 25-oct-2006 5 table 16: status register bits updated. 06-nov-2006 6 dq7 was replaced by dq7 for ?write to buffer and program abort? in table 16: status register bits . 10-dec-2007 7 applied numonyx branding.
m29w128fh, m29w128fl 78/78 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, tradema rks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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